1. Field of The Invention
The present invention concerns a power supply device and method with a power factor correction circuit.
2. Description of the Related Art
A switching mode power supply device exemplary of contemporary practice in the art generally includes a rectifier circuit for rectifying an alternating current voltage (AC) voltage into a ripple voltage, a power factor correction (PFC) circuit connected between the rectifier circuit and a load with a power saving mode to correct the power factor of the output voltage, and a pulse width modulation (PWM) circuit. The power saving mode of the load is achieved by apower saving mode control circuit such as display power management system (DPMS) connected to the load.
A power factor correction circuit exemplary of contemporary practice in the art includes a power factor correction (PFC) controller, a switching transistor, and a booster transformer for boosting the output voltage of the rectifier circuit, which consists of bridge diodes, according to the turning on/off of the switching transistor. In this case, the rectifier circuit is to convert an alternating current voltage (AC voltage) into a direct current voltage (DC voltage) of a ripple waveform. The supplied AC voltage, for example, is about 90V to 260V. Additionally provided are a diode for rectifying the voltage induced in the primary coil of the boost transformer, a smoothing capacitor and a voltage divider for regulating the output voltage of the power factor correction (PFC) circuit.
In the normal mode of the power supply device, the rectifier circuit supplies a direct voltage to the power factor correction (PFC) circuit, where the output DC voltage comes to have a value of about 400V according to the on/off operation of the switching transistor. The output is applied to the PWM control circuit, thereby securing the normal operation of the main power supply circuit. When the load such as an electronic apparatus is set to the power saving mode by a microprocessor or display power management system (DPMS), the duty ratio of the output pulses of the pulse width modulation (PWM) control circuit becomes much lower than in the normal mode, so that the load is supplied with the minimum power required only to operate the control circuit for controlling the power saving mode. However, the circuit exemplary of contemporary practice in the art requires the continuous operation of the power factor correction (PFC) circuit even in the power saving mode, thus causing power consumption due to the turning on/off of the switching transistor.
U.S. Pat. No. 5,515,261 to Bogdan entitled Power Factor Correction Circuitry, discloses a power factor correction circuit for use with a power supply. It is disclosed that the power supply has an input for receiving an AC input signal, a rectifier for producing a rectified AC signal and an output stage for outputting a DC output signal for driving a load coupled to the output stage. The power factor correction circuit comprises an input port coupled to the rectifier for receiving the rectified AC signal; and an inductor coupled to the input port for storing energy in response to excitation by the rectified AC signal. The excitation of the inductor is controlled through the opening the closing of a switch by a controller. A capacitor is coupled to the inductor and charged by the energy stored in the inductor when the switch is opened to produce the DC output signal. The power factor correction circuit includes a diode for blocking the charge path between the input port and the capacitor and also allowing the controller to boost the charge level on the capacitor.
U.S. Pat. No. 5,568,041 to Hesterman entitled Low-cost Power Factor Correction Circuit and Method for Electronic Ballasts, discloses apower factor corrected electronic ballast circuit. An embodiment includes a discontinuous conduction mode boost power factor correction circuit that is controlled with a simple pulse-width modulator (PWM) circuit comprising a few discrete components instead of an integrated circuit. The PWM circuit unitizes a reference waveform signal derived from the ballast inverter. The reference waveform is combined with a feedback signal to create a composite signal that is compared with a reference voltage to create a pulse-width-modulated signal. The feedback signal is used to regulate the bulk DC voltage. In an alternative embodiment, a feed forward signal that is proportional to the time-varying level of the rectified line voltage is added to the reference waveform and the feedback signal, and serves to modulate the pulse width of the boost circuit in a manner that reduces the harmonic distortion of the input current. In addition to the boost circuit, the power factor correction circuit can be realized with flyback and buck-boost topologies.
U.S. Pat. No. 5, 612,609 to Choi entitled Continuous Conduction Mode Switching Power Supply with Improved Power Factor Correction, disclosed a power factor correction circuit in which an inductor current is detected separately as a charging current indication signal and a discharging current indication signal by using a current sense resistor and a current sense circuit. It is disclosed a scaled-down output DC voltage is compared with a predetermined reference DC voltage by using an error amplifier which serves to produce an output voltage error signal. The output voltage error signal is then multiplied with a divided-down rectified input line voltage through the use of the multiplier to generate a sinusoidal reference signal. The sinusoidal reference signal is used by peak and valley comparators which also receive the charging and the discharging current indication signals. The outputs from the peak and the valley comparators are used to control a FET transistor which controls the input line current.
U.S. Pat. No. 5,644,214 to Lee entitled Power Factor Correction Circuit, discloses a continuous current type power factor correction circuit in a power device having rectifying means for rectifying an alternating current, a booster converter having an inductor, a diode and capacitor series connected to an output terminal of the rectifying means, a control switch connected in parallel with the series connection of the diode and a capacitor, and a load connected across the capacitor for outputting a boosted direct current to the load according to switching operation of the control switch, and a power factor correction circuit controlling the switching operation of the control switch, the power factor correction circuit, comprising an off-time controller comparing a first voltage signal with a second voltage signal and generating an off signal in response to the comparison, an on-time controller generating an on signal in accordance with a charge time period of the capacitor, the charge time period being determined from a point in time wherein the off-time controller generates the off signal, and a drive signal generator, respectively receiving the off and on signals, latching the off and on signals, and generating a drive signal which controls operation of the control switch.
U.S. Pat. No. 5,726,871 to Choi entitled Power Supply Circuit with Power Saving Mode for Video Display Appliance, discloses a power supply circuit for a video display appliance capable of reducing even the unnecessary power consumption caused by a power factor correction circuit when a display control for power saving is performed. It is disclosed that the power supply circuit includes a rectifying section, a power factor correction section. an SMPS, a control section for determining whether to perform a display control for power saving of the video display appliance to provide a control signal, and a switching section for controlling the operation of the power factor correction section according to the control signal provided from the control section.
U.S. Pat. No. 5,757,166 to Sodhi entitled Power Factor Correction Controlled Boost Converter with an Improved Zero Current Detection Circuit for Operation under High Input Voltage Conditions, discloses an electronic power supply circuit having a rectifier circuit adapted to receive a source of alternating current, a power factor correction driven boost converter, and a bulk capcitance. It is disclosed the boost converter includes a boost transformer having a primary winding and a secondary winding, a boost switch, a boost diode, a zener diode, and a power factor correction control circuit having a zero current detect input. The presence of the zener diode effectively adds a fixed offset to the voltage provided to the zero current detect input, thereby allowing the boost converter to operate under high input line voltage conditions. The zener diode can be oriented in various ways, and can be incorporated into an integrated circuit containing other elements of the power factor correction control circuit. One particular embodiment of the power supply circuit is for use in an electronic ballast for fluorescent lamps.
U.S. Pat. No. 5,757,635 to Seong entitled Power Factor Correction Circuit and Circuit Therefor Having Sense-FET and Boost Converter Control Circuit, discloses a power factor correction circuit including a boost converter, a zero-current detector for detecting a period in which an inductor current is zero, a half-wave rectifier for supplying a power voltage proportional to an output voltage of the boost converter, a control voltage generator for generating a control voltage to control the turn-on time timing of a sense-FET, a turn-on controller for making constant a turn-on duration of the sense-FET, an over current detector for generating a signal when a mirror terminal current of the sense-FET is greater than a predetermined current, an OR gate for performing a logic OR operation of the output signals of the turn-on controller and the over current detector, an output current controller for generating a gate drive signal of the sense-FET, and an under voltage lock out for turning off the power voltage when the power voltage is less than a predetermined voltage. This circuit enables an external pin count to be reduced by having a built-in boost converter controller and a built-in sense-FET in a single package.
U.S. Pat. No. 5,764,039 to Choi entitled Power Factor Correction Circuit Having Indirect Input Voltage Sensing, discloses a power factor correction circuit for a boost-type voltage converter determines the input voltage by sensing the rate at which the current through an inductor changes when a switching transistor is turned on. The circuit includes a current sense circuit which generates a control signal in response to the current flowing in the inductor. The control signal is compared with a sawtooth signal to control the input current waveform. It is disclosed an output detecting circuit generates a comparison reference signal for regulating the output voltage of the converter. The comparison reference signal is summed with the control signal to provide a comparison signal. A comparison circuit compares the comparison signal with the sawtooth signal and generates a pulse width modulated signal for controlling the switch. A compensation signal generator generates a compensated comparison signal in response to a ripple component in the output signal of the converter. The compensated comparison signal is summed with the sawtooth signal to compensate for distortion in the input current, thereby increasing the power factor. An amplifier in the sense circuit allows a low value sense resistor to be used.